GLinkGtx7FixedLat Entity Reference

Inheritance diagram for GLinkGtx7FixedLat:

Collaboration diagram for GLinkGtx7FixedLat:

Entities
GLinkGtx7FixedLat.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
GlinkPkg

Generics
FLAGSEL_G	boolean := false
SYNTH_TX_G	boolean := true
SYNTH_RX_G	boolean := true
TPD_G	time := 1 ns
SIM_GTRESET_SPEEDUP_G	string := " FALSE "
SIM_VERSION_G	string := " 4.0 "
SIMULATION_G	boolean := false
CPLL_REFCLK_SEL_G	bit_vector := " 001 "
CPLL_FBDIV_G	integer := 4
CPLL_FBDIV_45_G	integer := 5
CPLL_REFCLK_DIV_G	integer := 1
RXOUT_DIV_G	integer := 2
TXOUT_DIV_G	integer := 2
RX_CLK25_DIV_G	integer := 5
TX_CLK25_DIV_G	integer := 5
RX_OS_CFG_G	bit_vector := " 0000010000000 "
RXCDR_CFG_G	bit_vector := x " 03000023FF40200020 "
RX_DFE_KL_CFG2_G	bit_vector := x " 3008E56A "
RX_CM_TRIM_G	bit_vector := " 010 "
RX_DFE_LPM_CFG_G	bit_vector := x " 0954 "
RXDFELFOVRDEN_G	sl := ' 1 '
RXDFEXYDEN_G	sl := ' 1 '
TX_PLL_G	string := " QPLL "
RX_PLL_G	string := " CPLL "

Ports
gLinkTx	in	GLinkTxType
txReady	out	sl
gLinkTxClk	in	sl
gLinkTxClkEn	in	sl := ' 1 '
gLinkTxRst	in	sl := ' 0 '
gLinkRx	out	GLinkRxType
rxReady	out	sl
gLinkRxClk	in	sl
gLinkRxClkEn	in	sl := ' 1 '
gLinkRxRst	in	sl := ' 0 '
gLinkTxRefClk	in	sl
stableClk	in	sl
gtCPllRefClk	in	sl := ' 0 '
gtCPllLock	out	sl
gtQPllRefClk	in	sl := ' 0 '
gtQPllClk	in	sl := ' 0 '
gtQPllLock	in	sl := ' 0 '
gtQPllRefClkLost	in	sl := ' 0 '
gtQPllReset	out	sl
lpmMode	in	sl := ' 1 '
loopback	in	slv ( 2 downto 0 )
txPowerDown	in	sl
rxPowerDown	in	sl
rxClkDebug	out	sl
gtTxP	out	sl
gtTxN	out	sl
gtRxP	in	sl
gtRxN	in	sl

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The documentation for this design unit was generated from the following file:

• protocols/glink/gtx7/rtl/GLinkGtx7FixedLat.vhd