Pgp4TxLite Entity Reference

Inheritance diagram for Pgp4TxLite:

Collaboration diagram for Pgp4TxLite:

Entities
Pgp4TxLite.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>
Pgp4Pkg	Package <Pgp4Pkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
NUM_VC_G	integer range 1 to 16 := 1
SKIP_EN_G	boolean := false
FLOW_CTRL_EN_G	boolean := false

Ports
pgpTxClk	in	sl
pgpTxRst	in	sl
pgpTxIn	in	Pgp4TxInType := PGP4_TX_IN_INIT_C
pgpTxOut	out	Pgp4TxOutType
pgpTxActive	in	sl
pgpTxMasters	in	AxiStreamMasterArray ( NUM_VC_G- 1 downto 0 )
pgpTxSlaves	out	AxiStreamSlaveArray ( NUM_VC_G- 1 downto 0 )
locRxFifoCtrl	in	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
locRxLinkReady	in	sl := ' 1 '
remRxFifoCtrl	in	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
remRxLinkReady	in	sl := ' 1 '
phyTxActive	in	sl
phyTxReady	in	sl
phyTxValid	out	sl
phyTxStart	out	sl
phyTxData	out	slv ( 63 downto 0 )
phyTxHeader	out	slv ( 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4TxLite.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd