Pgp4TxLite.rtl Architecture Reference

Architecture >> Pgp4TxLite::rtl

Processes
DISABLE_SEL	( pgpTxIn , syncRemRxFifoCtrl )
DISABLE_SEL	( pgpTxIn , syncRemRxFifoCtrl )

Signals
syncLocRxFifoCtrl	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
syncLocRxLinkReady	sl
syncRemRxFifoCtrl	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
syncRemRxLinkReady	sl
disableSel	slv ( NUM_VC_G- 1 downto 0 )
rearbitrate	sl := ' 0 '
muxedTxMaster	AxiStreamMasterType
muxedTxSlave	AxiStreamSlaveType
phyTxActiveL	sl
protTxValid	sl
protTxReady	sl
protTxStart	sl
protTxData	slv ( 63 downto 0 )
protTxHeader	slv ( 1 downto 0 )

Instantiations
u_synchronizer_rem	Synchronizer <Entity Synchronizer>
u_synchronizervector_1	SynchronizerVector <Entity SynchronizerVector>
u_synchronizer_loc	Synchronizer <Entity Synchronizer>
u_synchronizer_pause	Synchronizer <Entity Synchronizer>
u_synchronizer_overflow	SynchronizerOneShot <Entity SynchronizerOneShot>
u_axistreammux_1	AxiStreamMux <Entity AxiStreamMux>
u_protocol	Pgp4TxLiteProtocol <Entity Pgp4TxLiteProtocol>
u_scrambler_1	Scrambler <Entity Scrambler>
u_synchronizer_rem	Synchronizer <Entity Synchronizer>
u_synchronizervector_1	SynchronizerVector <Entity SynchronizerVector>
u_synchronizer_loc	Synchronizer <Entity Synchronizer>
u_synchronizer_pause	Synchronizer <Entity Synchronizer>
u_synchronizer_overflow	SynchronizerOneShot <Entity SynchronizerOneShot>
u_axistreammux_1	AxiStreamMux <Entity AxiStreamMux>
u_protocol	Pgp4TxLiteProtocol <Entity Pgp4TxLiteProtocol>
u_scrambler_1	Scrambler <Entity Scrambler>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4TxLite.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4TxLite.vhd