AxiStreamMux Entity Reference

Inheritance diagram for AxiStreamMux:

Collaboration diagram for AxiStreamMux:

Entities
AxiStreamMux.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
ArbiterPkg	Package <ArbiterPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
PIPE_STAGES_G	integer range 0 to 16 := 0
NUM_SLAVES_G	integer range 1 to 256 := 4
MODE_G	string := " INDEXED "
TDEST_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
TID_MODE_G	string := " PASSTHROUGH "
TID_ROUTES_G	Slv8Array := ( 0 = > " -------- " )
PRIORITY_G	IntegerArray := ( 0 = > 0 )
TDEST_LOW_G	integer range 0 to 7 := 0
ILEAVE_EN_G	boolean := false
ILEAVE_ON_NOTVALID_G	boolean := false
ILEAVE_REARB_G	natural range 0 to 4095 := 0
REARB_DELAY_G	boolean := true
FORCED_REARB_HOLD_G	boolean := false

Ports
axisClk	in	sl
axisRst	in	sl
disableSel	in	slv ( NUM_SLAVES_G- 1 downto 0 ) := ( others = > ' 0 ' )
rearbitrate	in	sl := ' 0 '
ileaveRearb	in	slv ( 11 downto 0 ) := toSlv ( ILEAVE_REARB_G , 12 )
sAxisMasters	in	AxiStreamMasterArray ( NUM_SLAVES_G- 1 downto 0 )
sAxisSlaves	out	AxiStreamSlaveArray ( NUM_SLAVES_G- 1 downto 0 )
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamMux.vhd
• build/SRC_VHDL/surf/AxiStreamMux.vhd