AxiStreamMux.rtl Architecture Reference

Architecture >> AxiStreamMux::rtl

Processes
ROUTE_TABLE_REMAP	( sAxisMasters )
PRIORITY_CONTROL	( disableSel , sAxisMasters )
comb	( axisRst , ileaveRearb , intDisableSel , pipeAxisSlave , r , rearbitrate , sAxisMastersTmp )
seq	( axisClk , axisRst )
ROUTE_TABLE_REMAP	( sAxisMasters )
PRIORITY_CONTROL	( disableSel , sAxisMasters )
comb	( axisRst , ileaveRearb , intDisableSel , pipeAxisSlave , r , rearbitrate , sAxisMastersTmp )
seq	( axisClk , axisRst )

Constants
DEST_SIZE_C	integer := bitSize ( NUM_SLAVES_G- 1 )
ARB_BITS_C	integer := 2 ** DEST_SIZE_C
REG_INIT_C	RegType := ( acks = > ( others = > ' 0 ' ) , ackNum = > toSlv ( NUM_SLAVES_G- 1 , DEST_SIZE_C ) , valid = > ' 0 ' , arbCnt = > ( others = > ' 0 ' ) , slaves = > ( others = > AXI_STREAM_SLAVE_INIT_C ) , master = > AXI_STREAM_MASTER_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
sAxisMastersTmp	AxiStreamMasterArray ( NUM_SLAVES_G- 1 downto 0 )
pipeAxisMaster	AxiStreamMasterType
pipeAxisSlave	AxiStreamSlaveType
intDisableSel	slv ( NUM_SLAVES_G- 1 downto 0 )

Records
RegType

Instantiations
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>
axistreampipeline_1	AxiStreamPipeline <Entity AxiStreamPipeline>

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/rtl/AxiStreamMux.vhd
• build/SRC_VHDL/surf/AxiStreamMux.vhd