Scrambler Entity Reference

Inheritance diagram for Scrambler:

Entities
Scrambler.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
DIRECTION_G	string := " SCRAMBLER "
DATA_WIDTH_G	integer := 64
SIDEBAND_WIDTH_G	integer := 2
BIT_REVERSE_IN_G	boolean := false
BIT_REVERSE_OUT_G	boolean := false
TAPS_G	IntegerArray := ( 0 = > 39 , 1 = > 58 )

Ports
clk	in	sl
rst	in	sl
inputValid	in	sl := ' 1 '
inputReady	out	sl
inputData	in	slv ( DATA_WIDTH_G- 1 downto 0 )
inputSideband	in	slv ( SIDEBAND_WIDTH_G- 1 downto 0 )
outputValid	out	sl
outputReady	in	sl := ' 1 '
outputData	out	slv ( DATA_WIDTH_G- 1 downto 0 )
outputSideband	out	slv ( SIDEBAND_WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/general/rtl/Scrambler.vhd
• build/SRC_VHDL/surf/Scrambler.vhd