Scrambler.rtl Architecture Reference

Architecture >> Scrambler::rtl

Processes
comb	( inputData , inputSideband , inputValid , outputReady , r , rst )
seq	( clk , rst )
comb	( inputData , inputSideband , inputValid , outputReady , r , rst )
seq	( clk , rst )

Constants
SCRAMBLER_WIDTH_C	integer := maximum ( TAPS_G )
REG_INIT_C	RegType := ( inputReady = > ' 0 ' , outputValid = > ' 0 ' , scrambler = > ( others = > ' 0 ' ) , outputData = > ( others = > ' 0 ' ) , outputSideband = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/general/rtl/Scrambler.vhd
• build/SRC_VHDL/surf/Scrambler.vhd