Pgp4TxLiteProtocol Entity Reference

Inheritance diagram for Pgp4TxLiteProtocol:

Collaboration diagram for Pgp4TxLiteProtocol:

Entities
Pgp4TxLiteProtocol.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiStreamPacketizer2Pkg	Package <AxiStreamPacketizer2Pkg>
SsiPkg	Package <SsiPkg>
Pgp4Pkg	Package <Pgp4Pkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
NUM_VC_G	integer range 1 to 16 := 1
SKIP_EN_G	boolean := false
FLOW_CTRL_EN_G	boolean := false
STARTUP_HOLD_G	integer := 0

Ports
pgpTxClk	in	sl
pgpTxRst	in	sl
pgpTxIn	in	Pgp4TxInType := PGP4_TX_IN_INIT_C
pgpTxOut	out	Pgp4TxOutType
pgpTxActive	in	sl := ' 1 '
pgpTxMaster	in	AxiStreamMasterType
pgpTxSlave	out	AxiStreamSlaveType
locRxFifoCtrl	in	AxiStreamCtrlArray ( NUM_VC_G- 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
locRxLinkReady	in	sl := ' 1 '
remRxLinkReady	in	sl := ' 1 '
phyTxActive	in	sl
protTxReady	in	sl
protTxValid	out	sl
protTxStart	out	sl
protTxData	out	slv ( 63 downto 0 )
protTxHeader	out	slv ( 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4TxLiteProtocol.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4TxLiteProtocol.vhd