AxiLiteRingBuffer Entity Reference

Inheritance diagram for AxiLiteRingBuffer:

Collaboration diagram for AxiLiteRingBuffer:

Entities
AxiLiteRingBuffer.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
EXT_CTRL_ONLY_G	boolean := false
MEMORY_TYPE_G	string := " block "
REG_EN_G	boolean := true
DATA_WIDTH_G	positive range 1 to 32 := 32
RAM_ADDR_WIDTH_G	positive range 1 to 19 := 10

Ports
dataClk	in	sl
dataRst	in	sl := ' 0 '
dataValid	in	sl := ' 1 '
dataValue	in	slv ( DATA_WIDTH_G- 1 downto 0 )
bufferEnable	in	sl := ' 0 '
bufferClear	in	sl := ' 0 '
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteRingBuffer.vhd
• build/SRC_VHDL/surf/AxiLiteRingBuffer.vhd