AxiLiteRingBuffer.rtl Architecture Reference

Architecture >> AxiLiteRingBuffer::rtl

Processes
dataComb	( axilBufferClear , axilBufferEnable , bufferClear , bufferEnable , dataR , dataRst , dataValid , dataValue )
dataSeq	( dataClk , dataRst )
axiComb	( axilFirstAddr , axilLength , axilR , axilRamRdData , axilReadMaster , axilRst , axilWriteMaster , extBufferClear , extBufferEnable )
axilseq	( axilClk , axilRst )
dataComb	( axilBufferClear , axilBufferEnable , bufferClear , bufferEnable , dataR , dataRst , dataValid , dataValue )
dataSeq	( dataClk , dataRst )
axiComb	( axilFirstAddr , axilLength , axilR , axilRamRdData , axilReadMaster , axilRst , axilWriteMaster , extBufferClear , extBufferEnable )
axilseq	( axilClk , axilRst )

Constants
DATA_REG_INIT_C	DataRegType := ( ramWrEn = > ' 0 ' , ramWrData = > ( others = > ' 0 ' ) , bufferLength = > ( others = > ' 0 ' ) , firstAddr = > ( others = > ' 0 ' ) , nextAddr = > ( others = > ' 0 ' ) )
AXIL_ADDR_WIDTH_C	integer := RAM_ADDR_WIDTH_G+ 3
AXIL_REG_INIT_C	AxilRegType := ( bufferEnable = > ' 0 ' , bufferClear = > ' 0 ' , ramRdAddr = > ( others = > ' 0 ' ) , axilRdEn = > " 000 " , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
dataR	DataRegType := DATA_REG_INIT_C
dataRin	DataRegType
axilBufferEnable	sl
axilBufferClear	sl
axilR	AxilRegType := AXIL_REG_INIT_C
axilRin	AxilRegType
axilRamRdData	slv ( DATA_WIDTH_G- 1 downto 0 )
axilFirstAddr	slv ( RAM_ADDR_WIDTH_G- 1 downto 0 )
axilLength	slv ( RAM_ADDR_WIDTH_G- 1 downto 0 )
extBufferEnable	sl
extBufferClear	sl

Records
DataRegType
AxilRegType

Instantiations
dualportram_1	DualPortRam <Entity DualPortRam>
synchronizer_bufferen	Synchronizer <Entity Synchronizer>
synchronizer_bufferclear	SynchronizerOneShot <Entity SynchronizerOneShot>
synchronizerfifo_1	SynchronizerFifo <Entity SynchronizerFifo>
synchronizerfifo_2	SynchronizerFifo <Entity SynchronizerFifo>
synchronizer_databufferen	Synchronizer <Entity Synchronizer>
synchronizer_databufferclr	Synchronizer <Entity Synchronizer>
dualportram_1	DualPortRam <Entity DualPortRam>
synchronizer_bufferen	Synchronizer <Entity Synchronizer>
synchronizer_bufferclear	SynchronizerOneShot <Entity SynchronizerOneShot>
synchronizerfifo_1	SynchronizerFifo <Entity SynchronizerFifo>
synchronizerfifo_2	SynchronizerFifo <Entity SynchronizerFifo>
synchronizer_databufferen	Synchronizer <Entity Synchronizer>
synchronizer_databufferclr	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following files:

• axi/axi-lite/rtl/AxiLiteRingBuffer.vhd
• build/SRC_VHDL/surf/AxiLiteRingBuffer.vhd