SsiPrbsRx Entity Reference

Inheritance diagram for SsiPrbsRx:

Collaboration diagram for SsiPrbsRx:

Entities
SsiPrbsRx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
SsiPkg	Package <SsiPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32
SLAVE_READY_EN_G	boolean := true
GEN_SYNC_FIFO_G	boolean := false
CASCADE_SIZE_G	positive := 1
FIFO_ADDR_WIDTH_G	positive := 9
FIFO_PAUSE_THRESH_G	positive := 2 ** 8
SYNTH_MODE_G	string := " inferred "
MEMORY_TYPE_G	string := " block "
FIFO_INT_WIDTH_SELECT_G	string := " WIDE "
PRBS_SEED_SIZE_G	positive range 32 to 512 := 32
PRBS_TAPS_G	NaturalArray := ( 0 = > 31 , 1 = > 6 , 2 = > 2 , 3 = > 1 )
SLAVE_AXI_STREAM_CONFIG_G	AxiStreamConfigType
SLAVE_AXI_PIPE_STAGES_G	natural := 0

Ports
sAxisClk	in	sl
sAxisRst	in	sl := ' 0 '
sAxisMaster	in	AxiStreamMasterType
sAxisSlave	out	AxiStreamSlaveType
sAxisCtrl	out	AxiStreamCtrlType
mAxisMaster	out	AxiStreamMasterType
mAxisSlave	in	AxiStreamSlaveType := AXI_STREAM_SLAVE_FORCE_C
axiClk	in	sl := ' 0 '
axiRst	in	sl := ' 0 '
axiReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axiWriteSlave	out	AxiLiteWriteSlaveType
updatedResults	out	sl
errorDet	out	sl
busy	out	sl
errMissedPacket	out	sl
errLength	out	sl
errDataBus	out	sl
errEofe	out	sl
errWordCnt	out	slv ( 31 downto 0 )
packetRate	out	slv ( 31 downto 0 )
packetLength	out	slv ( 31 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiPrbsRx.vhd
• protocols/ssi/rtl/SsiPrbsRx.vhd