Architecture >> SsiPrbsRx::rtl

Processes
comb	( bypCheck , r , rxAxisMaster , sAxisRst , txAxisSlave )
seq	( sAxisClk , sAxisRst )
combAxiLite	( axiReadMaster , axiRst , axiWriteMaster , errDataBusCnt , errDataBusSync , errEofeCnt , errEofeSync , errLengthCnt , errLengthSync , errMissedPacketCnt , errMissedPacketSync , errWordCntSync , errWordStrbCnt , errWordStrbSync , frameCnt , overflow , overflow0Cnt , overflow1Cnt , packetLengthSync , packetRateSync , pause , pause0Cnt , pause1Cnt , rAxiLite )
seqAxiLite	( axiClk , axiRst )

Constants
MAX_CNT_C	slv ( 31 downto 0 ) := ( others = > ' 1 ' )
EVENT_CNT_SIZE_C	integer := minimum ( PRBS_SEED_SIZE_G , 32 )
PRBS_BYTES_C	natural := wordCount ( PRBS_SEED_SIZE_G , 8 )
PRBS_SSI_CONFIG_C	AxiStreamConfigType := ( TSTRB_EN_C = > false , TDATA_BYTES_C = > PRBS_BYTES_C , TDEST_BITS_C = > 8 , TID_BITS_C = > 8 , TKEEP_MODE_C = > TKEEP_COMP_C , TUSER_BITS_C = > 8 , TUSER_MODE_C = > TUSER_FIRST_LAST_C )
REG_INIT_C	RegType := ( busy = > ' 1 ' , packetLength = > toSlv ( 2 , 32 ) , errorDet = > ' 0 ' , eofe = > ' 0 ' , errLength = > ' 0 ' , updatedResults = > ' 0 ' , errMissedPacket = > ' 0 ' , errDataBus = > ' 0 ' , errWordStrb = > ' 0 ' , txCnt = > ( others = > ' 0 ' ) , bitPntr = > ( others = > ' 0 ' ) , errorBits = > ( others = > ' 0 ' ) , errWordCnt = > ( others = > ' 0 ' ) , eventCnt = > toSlv ( 1 , EVENT_CNT_SIZE_C ) , randomData = > ( others = > ' 0 ' ) , dataCnt = > ( others = > ' 0 ' ) , stopTime = > ( others = > ' 0 ' ) , startTime = > ( others = > ' 1 ' ) , packetRate = > ( others = > ' 1 ' ) , rxAxisSlave = > AXI_STREAM_SLAVE_INIT_C , txAxisMaster = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )
STATUS_SIZE_C	positive := 11
LOC_REG_INIT_C	LocRegType := ( cntRst = > ' 1 ' , bypCheck = > ' 0 ' , dummy = > ( others = > ' 0 ' ) , rollOverEn = > ( others = > ' 0 ' ) , axiReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axiWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , LENGTH_S , DATA_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
rxAxisMaster	AxiStreamMasterType
rxAxisSlave	AxiStreamSlaveType
txAxisMaster	AxiStreamMasterType
txAxisSlave	AxiStreamSlaveType
bypCheck	sl
axisCtrl	AxiStreamCtrlArray ( 1 downto 0 ) := ( others = > AXI_STREAM_CTRL_UNUSED_C )
rAxiLite	LocRegType := LOC_REG_INIT_C
rinAxiLite	LocRegType
updatedResultsSync	sl
errBitStrbSync	sl
errWordStrbSync	sl
errDataBusSync	sl
errEofeSync	sl
errLengthSync	sl
errMissedPacketSync	sl
overflow	slv ( 1 downto 0 )
pause	slv ( 1 downto 0 )
cntOut	SlVectorArray ( STATUS_SIZE_C- 1 downto 0 , STATUS_CNT_WIDTH_G- 1 downto 0 )
packetLengthSync	slv ( 31 downto 0 )
packetRateSync	slv ( 31 downto 0 )
errWordCntSync	slv ( 31 downto 0 )
frameCnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
pause1Cnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
overflow1Cnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
pause0Cnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
overflow0Cnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
errWordStrbCnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
errDataBusCnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
errEofeCnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
errLengthCnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )
errMissedPacketCnt	slv ( STATUS_CNT_WIDTH_G- 1 downto 0 )

Instantiations
axistreamfifo_rx	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_tx	AxiStreamGearbox <Entity AxiStreamGearbox>
u_bypcheck	Synchronizer <Entity Synchronizer>
syncfifo_inst	SynchronizerFifo <Entity SynchronizerFifo>
syncstatusvec_inst	SyncStatusVector <Entity SyncStatusVector>

The documentation for this design unit was generated from the following file:

Processes

Constants