SyncStatusVector Entity Reference

Inheritance diagram for SyncStatusVector:

Collaboration diagram for SyncStatusVector:

Entities
SyncStatusVector.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
COMMON_CLK_G	boolean := false
SYNC_STAGES_G	positive := 3
IN_POLARITY_G	slv := " 1 "
OUT_POLARITY_G	sl := ' 1 '
USE_DSP_G	string := " no "
SYNTH_CNT_G	slv := " 1 "
CNT_RST_EDGE_G	boolean := true
CNT_WIDTH_G	positive := 32
WIDTH_G	positive := 16

Ports
statusIn	in	slv ( WIDTH_G- 1 downto 0 )
statusOut	out	slv ( WIDTH_G- 1 downto 0 )
cntRstIn	in	sl
rollOverEnIn	in	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
cntOut	out	SlVectorArray ( WIDTH_G- 1 downto 0 , CNT_WIDTH_G- 1 downto 0 )
irqEnIn	in	slv ( WIDTH_G- 1 downto 0 ) := ( others = > ' 0 ' )
irqOut	out	sl
wrClk	in	sl
wrRst	in	sl := ' 0 '
rdClk	in	sl
rdRst	in	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncStatusVector.vhd
• build/SRC_VHDL/surf/SyncStatusVector.vhd