AsyncGearbox Entity Reference

Inheritance diagram for AsyncGearbox:

Collaboration diagram for AsyncGearbox:

Entities
AsyncGearbox.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 1 '
RST_ASYNC_G	boolean := false
SLAVE_WIDTH_G	positive
SLAVE_BIT_REVERSE_G	boolean := false
MASTER_WIDTH_G	positive
MASTER_BIT_REVERSE_G	boolean := false
EN_EXT_CTRL_G	boolean := true
INPUT_PIPE_STAGES_G	natural := 0
OUTPUT_PIPE_STAGES_G	natural := 0
FIFO_MEMORY_TYPE_G	string := " distributed "
FIFO_ADDR_WIDTH_G	positive := 4

Ports
slaveClk	in	sl
slaveRst	in	sl
slaveData	in	slv ( SLAVE_WIDTH_G- 1 downto 0 )
slaveValid	in	sl := ' 1 '
slaveReady	out	sl
slaveBitOrder	in	sl := ite ( SLAVE_BIT_REVERSE_G , ' 1 ' , ' 0 ' )
slip	in	sl := ' 0 '
masterClk	in	sl
masterRst	in	sl
masterData	out	slv ( MASTER_WIDTH_G- 1 downto 0 )
masterValid	out	sl
masterReady	in	sl := ' 1 '
masterBitOrder	in	sl := ite ( MASTER_BIT_REVERSE_G , ' 1 ' , ' 0 ' )

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The documentation for this design unit was generated from the following files:

• base/general/rtl/AsyncGearbox.vhd
• build/SRC_VHDL/surf/AsyncGearbox.vhd