AsyncGearbox.mapping Architecture Reference

Architecture >> AsyncGearbox::mapping

Constants
SLAVE_FASTER_C	boolean := SLAVE_WIDTH_G< = MASTER_WIDTH_G

Signals
fastClk	sl
fastRst	sl
gearboxDataIn	slv ( SLAVE_WIDTH_G- 1 downto 0 )
gearboxValidIn	sl
gearboxReadyIn	sl
gearboxDataOut	slv ( MASTER_WIDTH_G- 1 downto 0 )
gearboxValidOut	sl
gearboxReadyOut	sl
gearboxSlip	sl := ' 0 '
gearboxSlaveBitOrder	sl := ite ( SLAVE_BIT_REVERSE_G , ' 1 ' , ' 0 ' )
gearboxMasterBitOrder	sl := ite ( MASTER_BIT_REVERSE_G , ' 1 ' , ' 0 ' )
almostFull	sl
writeEnable	sl
asyncFifoRst	sl

Instantiations
u_slip	SynchronizerOneShot <Entity SynchronizerOneShot>
u_slavebitorder	Synchronizer <Entity Synchronizer>
u_masterbitorder	Synchronizer <Entity Synchronizer>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_input	FifoOutputPipeline <Entity FifoOutputPipeline>
u_gearbox_1	Gearbox <Entity Gearbox>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_output	FifoOutputPipeline <Entity FifoOutputPipeline>
u_slip	SynchronizerOneShot <Entity SynchronizerOneShot>
u_slavebitorder	Synchronizer <Entity Synchronizer>
u_masterbitorder	Synchronizer <Entity Synchronizer>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_input	FifoOutputPipeline <Entity FifoOutputPipeline>
u_gearbox_1	Gearbox <Entity Gearbox>
u_fifoasync_1	FifoAsync <Entity FifoAsync>
u_output	FifoOutputPipeline <Entity FifoOutputPipeline>

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The documentation for this design unit was generated from the following files:

• base/general/rtl/AsyncGearbox.vhd
• build/SRC_VHDL/surf/AsyncGearbox.vhd