Ad9249ReadoutGroup2 Entity Reference

Inheritance diagram for Ad9249ReadoutGroup2:

Collaboration diagram for Ad9249ReadoutGroup2:

Entities
Ad9249ReadoutGroup2.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
Ad9249Pkg	Package <Ad9249Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIM_DEVICE_G	string := " ULTRASCALE "
NUM_CHANNELS_G	natural := 8
SIMULATION_G	boolean := false
DEFAULT_DELAY_G	slv ( 8 downto 0 ) := " 000000000 "
ADC_INVERT_CH_G	slv ( 7 downto 0 ) := " 00000000 "

Ports
axilClk	in	sl
axilRst	in	sl
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
adcClkRst	in	sl
adcSerial	in	Ad9249SerialGroupType
adcStreamClk	in	sl
adcStreams	out	AxiStreamMasterArray ( NUM_CHANNELS_G- 1 downto 0 ) := ( others = > axiStreamMasterInit ( AD9249_AXIS_CFG_G ) )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249ReadoutGroup2.vhd