SURF
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DeviceDna7Series Entity Reference
+ Inheritance diagram for DeviceDna7Series:
+ Collaboration diagram for DeviceDna7Series:

Entities

DeviceDna7Series.rtl  architecture
 

Libraries

ieee 
surf 
unisim 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
USE_SLOWCLK_G  boolean := false
BUFR_CLK_DIV_G  string := " 8 "
RST_POLARITY_G  sl := ' 1 '
SIM_DNA_VALUE_G  bit_vector := X " 000000000000000 "

Ports

clk   in   sl
rst   in   sl
slowClk   in   sl := ' 0 '
dnaValue   out   slv ( 55 downto 0 )
dnaValid   out   sl

The documentation for this design unit was generated from the following file: