Synchronizer.rtl Architecture Reference

Architecture >> Synchronizer::rtl

Processes
comb	( crossDomainSyncReg , dataIn )
seq	( clk , rst )
seq	( clk )
comb	( crossDomainSyncReg , dataIn )
seq	( clk , rst )
seq	( clk )

Constants
INIT_C	slv ( STAGES_G- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( STAGES_G ) , INIT_G )

Signals
crossDomainSyncReg	slv ( STAGES_G- 1 downto 0 ) := INIT_C
rin	slv ( STAGES_G- 1 downto 0 )

Attributes
ASYNC_REG	string
ASYNC_REG	signal is " TRUE "
syn_srlstyle	string
syn_srlstyle	signal is " registers "
MSGON	string
MSGON	signal is " FALSE "
shreg_extract	string
shreg_extract	signal is " no "
register_balancing	string
register_balancing	signal is " no "
altera_attribute	string
altera_attribute	signal is " -name AUTO_SHIFT_REGISTER_RECOGNITION OFF "

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/Synchronizer.vhd
• build/SRC_VHDL/surf/Synchronizer.vhd