Pgp3AxiL Entity Reference

Inheritance diagram for Pgp3AxiL:

Collaboration diagram for Pgp3AxiL:

Entities
Pgp3AxiL.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Pgp3Pkg	Package <Pgp3Pkg>

Generics
TPD_G	time := 1 ns
COMMON_TX_CLK_G	boolean := false
COMMON_RX_CLK_G	boolean := false
WRITE_EN_G	boolean := false
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
ERROR_CNT_WIDTH_G	natural range 1 to 32 := 8
AXIL_CLK_FREQ_G	real := 125 . 0E + 6

Ports
pgpTxClk	in	sl
pgpTxRst	in	sl
pgpTxIn	out	Pgp3TxInType
pgpTxOut	in	Pgp3TxOutType
locTxIn	in	Pgp3TxInType := PGP3_TX_IN_INIT_C
pgpRxClk	in	sl
pgpRxRst	in	sl
pgpRxIn	out	Pgp3RxInType
pgpRxOut	in	Pgp3RxOutType
locRxIn	in	Pgp3RxInType := PGP3_RX_IN_INIT_C
statusWord	out	slv ( 63 downto 0 )
statusSend	out	sl
phyRxClk	in	sl
txDiffCtrl	out	slv ( 4 downto 0 )
txPreCursor	out	slv ( 4 downto 0 )
txPostCursor	out	slv ( 4 downto 0 )
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp3AxiL.vhd
• protocols/pgp/pgp3/core/rtl/Pgp3AxiL.vhd