Jesd204bRx Entity Reference

Inheritance diagram for Jesd204bRx:

Collaboration diagram for Jesd204bRx:

Entities
Jesd204bRx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
GEN_ASYNC_G	boolean := false
TEST_G	boolean := false
F_G	positive := 2
K_G	positive := 32
L_G	positive range 1 to 32 := 2

Ports
axiClk	in	sl
axiRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType
sampleDataArr_o	out	sampleDataArray ( L_G- 1 downto 0 )
dataValidVec_o	out	slv ( L_G- 1 downto 0 )
devClk_i	in	sl
devRst_i	in	sl
sysRef_i	in	sl
sysRefDbg_o	out	sl
r_jesdGtRxArr	in	jesdGtRxLaneTypeArray ( L_G- 1 downto 0 )
gtRxReset_o	out	slv ( L_G- 1 downto 0 )
rxPowerDown	out	slv ( L_G- 1 downto 0 )
rxPolarity	out	slv ( L_G- 1 downto 0 )
nSync_o	out	sl
pulse_o	out	slv ( L_G- 1 downto 0 )
leds_o	out	slv ( 1 downto 0 )

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Jesd204bRx.vhd
• protocols/jesd204b/rtl/Jesd204bRx.vhd