Jesd204bRx.rtl Architecture Reference

Architecture >> Jesd204bRx::rtl

Processes
PROCESS_115	( devClk_i )
comb	( devRst_i , s_nSyncAny )
seq	( devClk_i )
PROCESS_254	( devClk_i )
comb	( devRst_i , s_nSyncAny )
seq	( devClk_i )

Constants
REG_INIT_C	RegType := ( nSyncAnyD1 = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
s_lmfc	sl
s_nSyncVec	slv ( L_G- 1 downto 0 )
s_nSyncVecEn	slv ( L_G- 1 downto 0 )
s_dataValidVec	slv ( L_G- 1 downto 0 )
s_nSyncAll	sl
s_nSyncAny	sl
s_sysrefDlyRx	slv ( SYSRF_DLY_WIDTH_C- 1 downto 0 )
s_enableRx	slv ( L_G- 1 downto 0 )
s_replEnable	sl
s_scrEnable	sl
s_invertData	slv ( L_G- 1 downto 0 )
s_subClass	sl
s_gtReset	sl
s_invertSync	sl
s_clearErr	sl
s_statusRxArr	rxStatuRegisterArray ( L_G- 1 downto 0 )
s_thresoldHighArr	Slv16Array ( L_G- 1 downto 0 )
s_thresoldLowArr	Slv16Array ( L_G- 1 downto 0 )
s_dlyTxArr	Slv4Array ( L_G- 1 downto 0 )
s_alignTxArr	alignTxArray ( L_G- 1 downto 0 )
s_sampleDataArr	sampleDataArray ( L_G- 1 downto 0 )
s_sysrefSync	sl
s_sysrefD	sl
s_sysrefRe	sl
s_jesdGtRxArr	jesdGtRxLaneTypeArray ( L_G- 1 downto 0 )
s_rawData	slv32Array ( L_G- 1 downto 0 )
s_linkErrMask	slv ( 5 downto 0 )

Records
RegType

Instantiations
u_reg	JesdRxReg <Entity JesdRxReg>
jesdtxtest_inst	JesdTxTest <Entity JesdTxTest>
synchronizer_inst	Synchronizer <Entity Synchronizer>
u_sysrefdly	SlvDelay <Entity SlvDelay>
lmfcgen_inst	JesdLmfcGen <Entity JesdLmfcGen>
jesdrx_inst	JesdRxLane <Entity JesdRxLane>
pulser_inst	JesdTestSigGen <Entity JesdTestSigGen>
u_reg	JesdRxReg <Entity JesdRxReg>
jesdtxtest_inst	JesdTxTest <Entity JesdTxTest>
synchronizer_inst	Synchronizer <Entity Synchronizer>
u_sysrefdly	SlvDelay <Entity SlvDelay>
lmfcgen_inst	JesdLmfcGen <Entity JesdLmfcGen>
jesdrx_inst	JesdRxLane <Entity JesdRxLane>
pulser_inst	JesdTestSigGen <Entity JesdTestSigGen>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Jesd204bRx.vhd
• protocols/jesd204b/rtl/Jesd204bRx.vhd