JesdTxTest Entity Reference

Inheritance diagram for JesdTxTest:

Collaboration diagram for JesdTxTest:

Entities
JesdTxTest.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns

Ports
devClk_i	in	sl
devRst_i	in	sl
subClass_i	in	sl
enable_i	in	sl
lmfc_i	in	sl
nSync_i	in	sl
delay_i	in	slv ( 3 downto 0 )
align_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
txDataValid_o	out	sl
r_jesdGtRx	out	jesdGtRxLaneType

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTxTest.vhd
• protocols/jesd204b/rtl/JesdTxTest.vhd