JesdTxTest.rtl Architecture Reference

Architecture >> JesdTxTest::rtl

Processes
comb	( devRst_i , r , s_data , s_dataK )
seq	( devClk_i )
comb	( devRst_i , r , s_data , s_dataK )
seq	( devClk_i )

Constants
REG_INIT_C	RegType := ( dataD1 = > ( others = > ' 0 ' ) , dataKD1 = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
s_testCntr	slv ( 7 downto 0 )
s_dataValid	sl
s_align	sl
s_lmfc_dly	sl
s_nsync_dly	sl
s_dataK	slv ( r_jesdGtRx.dataK ' range )
s_data	slv ( r_jesdGtRx.data ' range )
s_data_sel	slv ( 1 downto 0 )

Records
RegType

Instantiations
lmfcdly_inst	SlvDelay <Entity SlvDelay>
nsyncdly_inst	SlvDelay <Entity SlvDelay>
syncfsm_inst	JesdSyncFsmTxTest <Entity JesdSyncFsmTxTest>
lmfcdly_inst	SlvDelay <Entity SlvDelay>
nsyncdly_inst	SlvDelay <Entity SlvDelay>
syncfsm_inst	JesdSyncFsmTxTest <Entity JesdSyncFsmTxTest>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTxTest.vhd
• protocols/jesd204b/rtl/JesdTxTest.vhd