JesdSyncFsmTxTest Entity Reference

Inheritance diagram for JesdSyncFsmTxTest:

Entities
JesdSyncFsmTxTest.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns

Ports
clk	in	sl
rst	in	sl
enable_i	in	sl
subClass_i	in	sl
lmfc_i	in	sl
nSync_i	in	sl
testCntr_o	out	slv ( 7 downto 0 )
dataValid_o	out	sl
align_o	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdSyncFsmTxTest.vhd
• protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd