JesdSyncFsmTxTest.rtl Architecture Reference

Architecture >> JesdSyncFsmTxTest::rtl

Processes
comb	( enable_i , lmfc_i , nSync_i , r , rst , subClass_i )
seq	( clk )
comb	( enable_i , lmfc_i , nSync_i , r , rst , subClass_i )
seq	( clk )

Constants
REG_INIT_C	RegType := ( dataValid = > ' 0 ' , align = > ' 0 ' , cnt = > ( others = > ' 0 ' ) , state = > IDLE_S )

Types
StateType	( IDLE_S , SYNC_S , ALIGN_S , DATA_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdSyncFsmTxTest.vhd
• protocols/jesd204b/rtl/JesdSyncFsmTxTest.vhd