JesdTestSigGen Entity Reference

Inheritance diagram for JesdTestSigGen:

Entities
JesdTestSigGen.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
F_G	positive := 2

Ports
clk	in	sl
rst	in	sl
enable_i	in	sl
thresoldLow_i	in	slv ( ( F_G* 8 ) - 1 downto 0 )
thresoldHigh_i	in	slv ( ( F_G* 8 ) - 1 downto 0 )
sampleData_i	in	slv ( ( GT_WORD_SIZE_C* 8 ) - 1 downto 0 )
testSig_o	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTestSigGen.vhd
• protocols/jesd204b/rtl/JesdTestSigGen.vhd