JesdTestSigGen.rtl Architecture Reference

Architecture >> JesdTestSigGen::rtl

Processes
comb	( enable_i , r , rst , s_sampleDataBr , thresoldHigh_i , thresoldLow_i )
seq	( clk )
comb	( enable_i , r , rst , s_sampleDataBr , thresoldHigh_i , thresoldLow_i )
seq	( clk )

Constants
REG_INIT_C	RegType := ( sig = > ' 0 ' )

Signals
r	RegType := REG_INIT_C
rin	RegType
s_sampleDataBr	slv ( sampleData_i )

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdTestSigGen.vhd
• protocols/jesd204b/rtl/JesdTestSigGen.vhd