JesdRxLane Entity Reference

Inheritance diagram for JesdRxLane:

Collaboration diagram for JesdRxLane:

Entities
JesdRxLane.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
F_G	positive := 2
K_G	positive := 32

Ports
devClk_i	in	sl
devRst_i	in	sl
subClass_i	in	sl
sysRef_i	in	sl
clearErr_i	in	sl
enable_i	in	sl
replEnable_i	in	sl
scrEnable_i	in	sl
status_o	out	slv ( ( RX_STAT_WIDTH_C ) - 1 downto 0 )
r_jesdGtRx	in	jesdGtRxLaneType
lmfc_i	in	sl
linkErrMask_i	in	slv ( 5 downto 0 ) := ( others = > ' 1 ' )
nSyncAny_i	in	sl
nSyncAnyD1_i	in	sl
inv_i	in	sl := ' 0 '
nSync_o	out	sl
dataValid_o	out	sl
sampleData_o	out	slv ( ( GT_WORD_SIZE_C* 8 ) - 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdRxLane.vhd
• protocols/jesd204b/rtl/JesdRxLane.vhd