JesdRxLane.rtl Architecture Reference

Architecture >> JesdRxLane::rtl

Processes
PROCESS_129	( devClk_i )
comb	( clearErr_i , enable_i , inv_i , r , r_jesdGtRx , s_bufWe , s_buffLatency , s_dataValidDly1 , s_errComb , s_kDetected , s_nSync , s_refDetected , s_sampleData , s_sampleDataValid )
seq	( devClk_i )
PROCESS_264	( devClk_i )
comb	( clearErr_i , enable_i , inv_i , r , r_jesdGtRx , s_bufWe , s_buffLatency , s_dataValidDly1 , s_errComb , s_kDetected , s_nSync , s_refDetected , s_sampleData , s_sampleDataValid )
seq	( devClk_i )

Constants
ERR_REG_WIDTH_C	positive := 4 + 2 * GT_WORD_SIZE_C
REG_INIT_C	RegType := ( bufWeD1 = > ' 0 ' , errReg = > ( others = > ' 0 ' ) , sampleData = > ( others = > ' 0 ' ) , sampleDataValid = > ' 0 ' , jesdGtRx = > JESD_GT_RX_LANE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
s_nSync	sl
s_readBuff	sl
s_alignFrame	sl
s_alignFrameDly1	sl
s_alignFrameDly0	sl
s_ila	sl
s_dataValid	sl
s_dataValidDly1	sl
s_dataValidDly0	sl
s_bufRst	sl
s_bufWe	sl
s_bufRe	sl
s_charAndData	slv ( ( ( GT_WORD_SIZE_C* 8 ) + GT_WORD_SIZE_C ) - 1 downto 0 )
s_charAndDataBuff	slv ( s_charAndData )
s_charAndDataBuffDly1	slv ( s_charAndData )
s_charAndDataBuffDly0	slv ( s_charAndData )
s_sampleData	slv ( sampleData_o )
s_sampleDataValid	sl
s_bufOvf	sl
s_bufUnf	sl
s_bufFull	sl
s_alignErr	sl
s_positionErr	sl
s_linkErrVec	slv ( 5 downto 0 )
s_linkErr	sl
s_kDetected	sl
s_refDetected	sl
s_errComb	slv ( ERR_REG_WIDTH_C- 1 downto 0 )
s_buffLatency	slv ( 7 downto 0 )

Records
RegType

Instantiations
rx_buffer_fifo_inst	FifoSync <Entity FifoSync>
syncfsm_inst	JesdSyncFsmRx <Entity JesdSyncFsmRx>
alignfrrepch_inst	JesdAlignFrRepCh <Entity JesdAlignFrRepCh>
rx_buffer_fifo_inst	FifoSync <Entity FifoSync>
syncfsm_inst	JesdSyncFsmRx <Entity JesdSyncFsmRx>
alignfrrepch_inst	JesdAlignFrRepCh <Entity JesdAlignFrRepCh>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdRxLane.vhd
• protocols/jesd204b/rtl/JesdRxLane.vhd