JesdSyncFsmRx Entity Reference

Inheritance diagram for JesdSyncFsmRx:

Entities
JesdSyncFsmRx.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
F_G	positive := 2
K_G	positive := 32
NUM_ILAS_MF_G	positive := 4

Ports
clk	in	sl
rst	in	sl
enable_i	in	sl
gtReady_i	in	sl
subClass_i	in	sl
sysRef_i	in	sl
dataRx_i	in	slv ( ( GT_WORD_SIZE_C* 8 ) - 1 downto 0 )
chariskRx_i	in	slv ( GT_WORD_SIZE_C- 1 downto 0 )
lmfc_i	in	sl
nSyncAny_i	in	sl
nSyncAnyD1_i	in	sl
linkErr_i	in	sl
nSync_o	out	sl
buffLatency_o	out	slv ( 7 downto 0 )
readBuff_o	out	sl
alignFrame_o	out	sl
ila_o	out	sl
kDetected_o	out	sl
sysref_o	out	sl
dataValid_o	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdSyncFsmRx.vhd
• protocols/jesd204b/rtl/JesdSyncFsmRx.vhd