JesdRxReg Entity Reference

Inheritance diagram for JesdRxReg:

Collaboration diagram for JesdRxReg:

Entities
JesdRxReg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Jesd204bPkg	Package <Jesd204bPkg>

Generics
TPD_G	time := 1 ns
AXI_ADDR_WIDTH_G	positive := 10
L_G	positive range 1 to 32 := 2

Ports
axiClk_i	in	sl
axiRst_i	in	sl
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
devClk_i	in	sl
devRst_i	in	sl
sysrefRe_i	in	sl
statusRxArr_i	in	rxStatuRegisterArray ( L_G- 1 downto 0 )
rawData_i	in	slv32Array ( L_G- 1 downto 0 )
sysrefDlyRx_o	out	slv ( SYSRF_DLY_WIDTH_C- 1 downto 0 )
enableRx_o	out	slv ( L_G- 1 downto 0 )
replEnable_o	out	sl
scrEnable_o	out	sl
invertData_o	out	slv ( L_G- 1 downto 0 )
dlyTxArr_o	out	Slv4Array ( L_G- 1 downto 0 )
alignTxArr_o	out	alignTxArray ( L_G- 1 downto 0 )
thresoldLowArr_o	out	Slv16Array ( L_G- 1 downto 0 )
thresoldHighArr_o	out	Slv16Array ( L_G- 1 downto 0 )
subClass_o	out	sl
gtReset_o	out	sl
clearErr_o	out	sl
invertSync_o	out	sl
linkErrMask_o	out	slv ( 5 downto 0 )
rxPowerDown	out	slv ( L_G- 1 downto 0 )
rxPolarity	out	slv ( L_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/JesdRxReg.vhd
• protocols/jesd204b/rtl/JesdRxReg.vhd