JesdRxReg.rtl Architecture Reference

Architecture >> JesdRxReg::rtl

Processes
comb	( axiRst_i , axilReadMaster , axilWriteMaster , r , s_RdAddr , s_WrAddr , s_rawData , s_statusCnt , s_statusRxArr , sysRefPeriodmax , sysRefPeriodmin )
seq	( axiClk_i )

Constants

REG_INIT_C

RegType := ( enableRx = > ( others = > ' 0 ' ) , invertData = > ( others = > ' 0 ' ) , commonCtrl = > " 010111 " , linkErrMask = > " 111111 " , sysrefDlyRx = > ( others = > ' 0 ' ) , testTXItf = > ( others = > x " 0000 " ) , testSigThr = > ( others = > x " A000_5000 " ) , rxPolarity = > ( others = > ' 0 ' ) , rxPowerDown = > ( others = > ' 0 ' ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType
s_RdAddr	natural := 0
s_WrAddr	natural := 0
s_statusRxArr	rxStatuRegisterArray ( L_G- 1 downto 0 )
s_rawData	slv32Array ( L_G- 1 downto 0 )
s_statusCnt	SlVectorArray ( L_G- 1 downto 0 , 31 downto 0 )
s_adcValids	slv ( L_G- 1 downto 0 )
sysrefDlyRx	slv ( SYSRF_DLY_WIDTH_C- 1 downto 0 )
enableRx	slv ( L_G- 1 downto 0 )
replEnable	sl
scrEnable	sl
invertData	slv ( L_G- 1 downto 0 )
dlyTxArr	Slv4Array ( L_G- 1 downto 0 )
alignTxArr	alignTxArray ( L_G- 1 downto 0 )
thresoldLowArr	Slv16Array ( L_G- 1 downto 0 )
thresoldHighArr	Slv16Array ( L_G- 1 downto 0 )
subClass	sl
gtReset	sl
clearErr	sl
invertSync	sl
linkErrMask	slv ( 5 downto 0 )
sysRefPeriodmin	slv ( 15 downto 0 )
sysRefPeriodmax	slv ( 15 downto 0 )

Records
RegType

Instantiations
u_jesdsysrefmon	JesdSysrefMon <Entity JesdSysrefMon>
u_syncstatusvector	SyncStatusVector <Entity SyncStatusVector>
u_statusrxarr	SynchronizerVector <Entity SynchronizerVector>
u_rawdata	SynchronizerFifo <Entity SynchronizerFifo>
u_sysrefdlyrx	SynchronizerVector <Entity SynchronizerVector>
u_sysrefdlyrx_pipeline	RstPipelineVector <Entity RstPipelineVector>
u_enablerx	SynchronizerVector <Entity SynchronizerVector>
u_enablerx_pipeline	RstPipelineVector <Entity RstPipelineVector>
u_subclass	Synchronizer <Entity Synchronizer>
u_subclass_pipeline	RstPipeline <Entity RstPipeline>
u_replenable	Synchronizer <Entity Synchronizer>
u_replenable_pipeline	RstPipeline <Entity RstPipeline>
u_gtreset	Synchronizer <Entity Synchronizer>
u_gtreset_pipeline	RstPipeline <Entity RstPipeline>
u_clearerr	Synchronizer <Entity Synchronizer>
u_clearerr_pipeline	RstPipeline <Entity RstPipeline>
u_invertsync	Synchronizer <Entity Synchronizer>
u_invertsync_pipeline	RstPipeline <Entity RstPipeline>
u_screnable	Synchronizer <Entity Synchronizer>
u_screnable_pipeline	RstPipeline <Entity RstPipeline>
u_linkerrmask	SynchronizerVector <Entity SynchronizerVector>
u_linkerrmask_pipeline	RstPipelineVector <Entity RstPipelineVector>
u_invertdata	SynchronizerVector <Entity SynchronizerVector>
u_invertdata_pipeline	RstPipelineVector <Entity RstPipelineVector>
u_dlytxarr	SynchronizerVector <Entity SynchronizerVector>
u_dlytxarr_pipeline	RstPipelineVector <Entity RstPipelineVector>
u_aligntxarr	SynchronizerVector <Entity SynchronizerVector>
u_aligntxarr_pipeline	RstPipelineVector <Entity RstPipelineVector>
u_thresoldlowarr_a	SynchronizerVector <Entity SynchronizerVector>
u_thresoldlowarr_a_pipeline	RstPipelineVector <Entity RstPipelineVector>
u_thresoldlowarr_b	SynchronizerVector <Entity SynchronizerVector>
u_thresoldlowarr_b_pipeline	RstPipelineVector <Entity RstPipelineVector>

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The documentation for this design unit was generated from the following file:

• protocols/jesd204b/rtl/JesdRxReg.vhd