RstPipelineVector Entity Reference

Inheritance diagram for RstPipelineVector:

Collaboration diagram for RstPipelineVector:

Entities
RstPipelineVector.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
INV_RST_G	boolean := false
PIPE_STAGES_G	positive := 3
MAX_FANOUT_G	positive := 16384
INIT_G	slv := " 1 "
WIDTH_G	positive := 16

Ports
clk	in	sl
rstIn	in	slv ( WIDTH_G- 1 downto 0 )
rstOut	out	slv ( WIDTH_G- 1 downto 0 )

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The documentation for this design unit was generated from the following files:

• base/general/rtl/RstPipelineVector.vhd
• build/SRC_VHDL/surf/RstPipelineVector.vhd