Pgp4AxiL Entity Reference

Inheritance diagram for Pgp4AxiL:

Collaboration diagram for Pgp4AxiL:

Entities
Pgp4AxiL.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
Pgp4Pkg	Package <Pgp4Pkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
COMMON_TX_CLK_G	boolean := false
COMMON_RX_CLK_G	boolean := false
WRITE_EN_G	boolean := true
NUM_VC_G	integer range 1 to 16 := 4
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 16
ERROR_CNT_WIDTH_G	natural range 1 to 16 := 8
TX_POLARITY_G	sl := ' 0 '
RX_POLARITY_G	sl := ' 0 '
PGP_FEC_ENABLE_G	boolean := false
AXIL_CLK_FREQ_G	real := 125 . 0E + 6

Ports
pgpTxClk	in	sl
pgpTxRst	in	sl
pgpTxIn	out	Pgp4TxInType
pgpTxOut	in	Pgp4TxOutType
locTxIn	in	Pgp4TxInType := PGP4_TX_IN_INIT_C
phyTxFecByp	out	sl
pgpRxClk	in	sl
pgpRxRst	in	sl
pgpRxIn	out	Pgp4RxInType
pgpRxOut	in	Pgp4RxOutType
locRxIn	in	Pgp4RxInType := PGP4_RX_IN_INIT_C
phyRxClk	in	sl
phyRxRst	in	sl
phyRxFecByp	out	sl
phyRxFecInjErr	out	sl := ' 0 '
phyRxFecLock	in	sl
phyRxFecCorInc	in	sl
phyRxFecUnCorInc	in	sl
txDiffCtrl	out	slv ( 4 downto 0 )
txPreCursor	out	slv ( 4 downto 0 )
txPostCursor	out	slv ( 4 downto 0 )
txPolarity	out	sl
rxPolarity	out	sl
axilClk	in	sl
axilRst	in	sl
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Pgp4AxiL.vhd
• protocols/pgp/pgp4/core/rtl/Pgp4AxiL.vhd