TenGigEthGth7Clk Entity Reference

Inheritance diagram for TenGigEthGth7Clk:

Collaboration diagram for TenGigEthGth7Clk:

Entities
TenGigEthGth7Clk.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
USE_GTREFCLK_G	boolean := false
REFCLK_DIV2_G	boolean := false
QPLL_REFCLK_SEL_G	bit_vector := " 001 "

Ports
extRst	in	sl
phyClk	out	sl
phyRst	out	sl
gtRefClk	in	sl := ' 0 '
gtClkP	in	sl := ' 1 '
gtClkN	in	sl := ' 0 '
qplllock	out	sl
qplloutclk	out	sl
qplloutrefclk	out	sl
qpllRst	in	sl

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd