TenGigEthGth7Clk.mapping Architecture Reference

Architecture >> TenGigEthGth7Clk::mapping

Constants
QPLL_REFCLK_SEL_C	bit_vector := ite ( USE_GTREFCLK_G , " 111 " , QPLL_REFCLK_SEL_G )

Signals
refClockDiv2	sl := ' 0 '
refClock	sl := ' 0 '
refClk	sl := ' 0 '
phyClock	sl := ' 0 '
phyReset	sl := ' 1 '
pwrUpRst	sl := ' 1 '
qpllReset	sl := ' 1 '

Instantiations
pwruprst_inst	PwrUpRst <Entity PwrUpRst>
synchronizer_0	Synchronizer <Entity Synchronizer>
ibufds_gte2_inst	ibufds_gte2
clk156_bufg	bufg
gth7quadpll_inst	Gth7QuadPll <Entity Gth7QuadPll>

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The documentation for this design unit was generated from the following file:

• ethernet/TenGigEthCore/gth7/rtl/TenGigEthGth7Clk.vhd