Ad9681Readout Entity Reference

Inheritance diagram for Ad9681Readout:

Collaboration diagram for Ad9681Readout:

Entities
Ad9681Readout.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
Ad9681Pkg	Package <Ad9681Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
IODELAY_GROUP_G	string := " DEFAULT_GROUP "
IDELAYCTRL_FREQ_G	real := 200 . 0
DEFAULT_DELAY_G	integer range 0 to 2 ** 5 - 1 := 0
INVERT_G	boolean := false
NEGATE_G	boolean := false

Ports
axilClk	in	sl
axilRst	in	sl
axilWriteMaster	in	AxiLiteWriteMasterType
axilWriteSlave	out	AxiLiteWriteSlaveType := AXI_LITE_WRITE_SLAVE_EMPTY_DECERR_C
axilReadMaster	in	AxiLiteReadMasterType
axilReadSlave	out	AxiLiteReadSlaveType := AXI_LITE_READ_SLAVE_EMPTY_DECERR_C
adcClkRst	in	sl
adcSerial	in	Ad9681SerialType
adcStreamClk	in	sl
adcStreams	out	AxiStreamMasterArray ( 7 downto 0 ) := ( others = > axiStreamMasterInit ( AD9681_AXIS_CFG_G ) )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Readout.vhd