- Generated by
1.9.8
|
SURF
|
Processes | |
| axilComb | ( adcFrameSync , axilR , axilReadMaster , axilRst , axilWriteMaster , curDelay , debugDataTmp , debugDataValid , errorDetCount , lockedFallCount , lockedSync ) |
| axilSeq | ( axilClk ) |
| adcComb | ( adcFrame , adcR ) |
| adcSeq | ( adcBitClkR , adcBitRst ) |
| GLUE_COMB | ( adcData , invertSync , locked , negateSync ) |
Constants | |
| NUM_CHANNELS_C | natural := 8 |
| AXIL_REG_INIT_C | AxilRegType := ( axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , usrDly = > ( others = > toSlv ( DEFAULT_DELAY_G , 5 ) ) , enUsrDly = > ' 0 ' , freezeDebug = > ' 0 ' , readoutDebug0 = > ( others = > ( others = > ' 0 ' ) ) , readoutDebug1 = > ( others = > ( others = > ' 0 ' ) ) , lockedCountRst = > ' 0 ' , invert = > toSl ( INVERT_G ) , negate = > toSl ( NEGATE_G ) , realign = > ' 1 ' , minEyeWidth = > X " 50 " ) |
| ADC_REG_INIT_C | AdcRegType := ( errorDet = > ' 0 ' ) |
Types | |
| AdcDataArray | array ( natural range <> ) of slv8Array ( 7 downto 0 ) |
| DelayDataArray | array ( natural range <> ) of slv5Array ( 7 downto 0 ) |
| AdcRegArray | array ( natural range <> ) of AdcRegType |
Signals | |
| lockedSync | slv ( 1 downto 0 ) |
| lockedFallCount | slv16Array ( 1 downto 0 ) |
| axilR | AxilRegType := AXIL_REG_INIT_C |
| axilRin | AxilRegType |
| adcR | AdcRegArray ( 1 downto 0 ) := ( others = > ADC_REG_INIT_C ) |
| adcRin | AdcRegArray ( 1 downto 0 ) |
| adcValid | slv ( 1 downto 0 ) |
| tmpAdcClk | slv ( 1 downto 0 ) |
| adcBitClkIo | slv ( 1 downto 0 ) |
| adcBitClkIoInv | slv ( 1 downto 0 ) |
| adcBitClkR | slv ( 1 downto 0 ) |
| adcBitRst | slv ( 1 downto 0 ) |
| adcFramePad | slv ( 1 downto 0 ) |
| adcFrame | slv8Array ( 1 downto 0 ) |
| adcFrameSync | slv8Array ( 1 downto 0 ) |
| adcDataPad | slv8Array ( 1 downto 0 ) |
| adcData | AdcDataArray ( 1 downto 0 ) |
| fifoWrData | slv16Array ( NUM_CHANNELS_C- 1 downto 0 ) |
| fifoDataValid | sl |
| fifoDataOut | slv ( NUM_CHANNELS_C* 16 - 1 downto 0 ) |
| fifoDataIn | slv ( NUM_CHANNELS_C* 16 - 1 downto 0 ) |
| fifoDataTmp | slv16Array ( NUM_CHANNELS_C- 1 downto 0 ) |
| debugDataValid | sl |
| debugDataOut | slv ( NUM_CHANNELS_C* 16 - 1 downto 0 ) |
| debugDataTmp | slv16Array ( NUM_CHANNELS_C- 1 downto 0 ) |
| invertSync | slv ( 1 downto 0 ) |
| negateSync | slv ( 1 downto 0 ) |
| bitSlip | slv ( 1 downto 0 ) |
| dlyLoad | slv ( 1 downto 0 ) |
| dlyCfg | Slv9Array ( 1 downto 0 ) |
| enUsrDlyCfg | slv ( 1 downto 0 ) |
| usrDlyCfg | slv9Array ( 1 downto 0 ) := ( others = > ( others = > ' 0 ' ) ) |
| minEyeWidthSync | slv8Array ( 1 downto 0 ) |
| lockingCntCfg | slv ( 23 downto 0 ) := ite ( SIMULATION_G , X " 000008 " , X " 00FFFF " ) |
| locked | slv ( 1 downto 0 ) |
| realignSync | slv ( 1 downto 0 ) |
| curDelay | slv5Array ( 1 downto 0 ) |
| errorDetCount | slv16Array ( 1 downto 0 ) |
| errorDet | slv ( 1 downto 0 ) |
Records | |
| AxilRegType | |
| AdcRegType | |
1.9.8