Ad9681Deserializer Entity Reference

Inheritance diagram for Ad9681Deserializer:

Entities
Ad9681Deserializer.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
DEFAULT_DELAY_G	natural := 0
IODELAY_GROUP_G	string
IDELAYCTRL_FREQ_G	real := 200 . 0

Ports
clkIo	in	sl
clkIoInv	in	sl
clkR	in	sl
rst	in	sl
slip	in	sl
sysClk	in	sl
curDelay	out	slv ( 4 downto 0 )
setDelay	in	slv ( 4 downto 0 )
setValid	in	sl
iData	in	sl
oData	out	slv ( 7 downto 0 )

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9681/7Series/rtl/Ad9681Deserializer.vhd