SelectIoRxGearboxAligner Entity Reference

Inheritance diagram for SelectIoRxGearboxAligner:

Entities
SelectIoRxGearboxAligner.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
SIMULATION_G	boolean := false
CODE_TYPE_G	string := " LINE_CODE "
DLY_STEP_SIZE_G	positive range 1 to 16 := 1

Ports
clk	in	sl
rst	in	sl
lineCodeValid	in	sl
lineCodeErr	in	sl
lineCodeDispErr	in	sl
linkOutOfSync	in	sl
rxHeaderValid	in	sl
rxHeader	in	slv ( 1 downto 0 )
bitSlip	out	sl
dlyLoad	out	sl
dlyCfg	out	slv ( 8 downto 0 )
enUsrDlyCfg	in	sl := ' 0 '
usrDlyCfg	in	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
bypFirstBerDet	in	sl := ' 1 '
minEyeWidth	in	slv ( 7 downto 0 ) := toSlv ( 80 , 8 )
lockingCntCfg	in	slv ( 23 downto 0 ) := ite ( SIMULATION_G , x " 00_0064 " , x " 00_FFFF " )
eyeWidth	out	slv ( 8 downto 0 )
errorDet	out	sl
locked	out	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SelectIoRxGearboxAligner.vhd
• xilinx/general/rtl/SelectIoRxGearboxAligner.vhd