SelectIoRxGearboxAligner.rtl Architecture Reference

Architecture >> SelectIoRxGearboxAligner::rtl

Processes
comb	( bypFirstBerDet , enUsrDlyCfg , lineCodeDispErr , lineCodeErr , lineCodeValid , linkOutOfSync , lockingCntCfg , minEyeWidth , r , rst , rxHeader , rxHeaderValid , usrDlyCfg )
seq	( clk )
comb	( bypFirstBerDet , enUsrDlyCfg , lineCodeDispErr , lineCodeErr , lineCodeValid , linkOutOfSync , lockingCntCfg , minEyeWidth , r , rst , rxHeader , rxHeaderValid , usrDlyCfg )
seq	( clk )

Procedures
	slipProcedure
	slipProcedure

Constants
SLIP_WAIT_C	positive := 100
REG_INIT_C	RegType := ( enUsrDlyCfg = > ' 0 ' , usrDlyCfg = > ( others = > ' 0 ' ) , dlyLoad = > ( others = > ' 0 ' ) , dlyConfig = > ( others = > ' 0 ' ) , dlyCache = > ( others = > ' 0 ' ) , slipWaitCnt = > 0 , goodCnt = > ( others = > ' 0 ' ) , bitSlip = > ' 0 ' , errorDet = > ' 0 ' , firstError = > ' 0 ' , armed = > ' 0 ' , scanDone = > ' 0 ' , eyeWidth = > ( others = > ' 0 ' ) , locked = > ' 0 ' , state = > UNLOCKED_S )

Types
StateType	( UNLOCKED_S , SLIP_WAIT_S , LOCKING_S , EYE_SCAN_S , BIT_WAIT_S , BIT_ALIGN_S , LOCKED_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

Shared Variables
scanCnt	slv ( 8 downto 0 )
scanHalf	slv ( 8 downto 0 )
eyescanCfg	slv ( 8 downto 0 )
valid	sl

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SelectIoRxGearboxAligner.vhd
• xilinx/general/rtl/SelectIoRxGearboxAligner.vhd