AxiAd9467Reg Entity Reference

Inheritance diagram for AxiAd9467Reg:

Collaboration diagram for AxiAd9467Reg:

Entities
AxiAd9467Reg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiAd9467Pkg	Package <AxiAd9467Pkg>

Generics
TPD_G	time := 1 ns
DEMUX_INIT_G	sl := ' 0 '
DELAY_INIT_G	Slv5Array ( 0 to 7 ) := ( others = > " 00000 " )
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32

Ports
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
status	in	AxiAd9467StatusType
config	out	AxiAd9467ConfigType
adcClk	in	sl
adcRst	in	sl
refClk200MHz	in	sl

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9467/rtl/AxiAd9467Reg.vhd