Architecture >> AxiAd9467Reg::rtl

Functions
slv	compressAddressSpace ( vec: in slv( 7 downto 0) )

Processes
comb	( axiReadMaster , axiRst , axiWriteMaster , r , syncIn )
seq	( axiClk )

Constants
REG_INIT_C	RegType := ( AXI_AD9467_CONFIG_INIT_C , IDLE_S , AXI_LITE_READ_SLAVE_INIT_C , AXI_LITE_WRITE_SLAVE_INIT_C )

Types
StateType	( IDLE_S , REQ_S , ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
syncIn	AxiAd9467StatusType := AXI_AD9467_STATUS_INIT_C

Records
RegType

Instantiations
syncin_delay_dmux	Synchronizer <Entity Synchronizer>
syncout_delayin_load	RstSync <Entity RstSync>
syncout_delayin_rst	RstSync <Entity RstSync>
syncout_delayin_data	SynchronizerFifo <Entity SynchronizerFifo>
syncin_plllocked	Synchronizer <Entity Synchronizer>
syncin_adcdatamon	SynchronizerFifo <Entity SynchronizerFifo>
syncin_delayout_rdy	Synchronizer <Entity Synchronizer>
syncin_delayout_data	SynchronizerFifo <Entity SynchronizerFifo>

The documentation for this design unit was generated from the following file:

Functions

Processes