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TenGigEthGtyUltraScaleRst Entity Reference
Inheritance diagram for TenGigEthGtyUltraScaleRst: Collaboration diagram for TenGigEthGtyUltraScaleRst:Entities | |
| TenGigEthGtyUltraScaleRst.rtl | architecture |
Libraries | |
| ieee | |
| surf | |
| unisim | |
Use Clauses | |
| std_logic_1164 | |
| std_logic_unsigned | |
| std_logic_arith | |
| StdRtlPkg | Package <StdRtlPkg> |
| vcomponents | |
Generics | |
| TPD_G | time := 1 ns |
Ports | ||
| coreClk | in | sl |
| coreRst | in | sl |
| txGtClk | in | sl |
| txRstdone | in | sl |
| rxRstdone | in | sl |
| phyClk | out | sl |
| phyRst | out | sl |
| phyReady | out | sl |
The documentation for this design unit was generated from the following file:
- ethernet/TenGigEthCore/gtyUltraScale+/rtl/TenGigEthGtyUltraScaleRst.vhd
