AxiLtc2270Reg Entity Reference

Inheritance diagram for AxiLtc2270Reg:

Collaboration diagram for AxiLtc2270Reg:

Entities
AxiLtc2270Reg.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiLtc2270Pkg	Package <AxiLtc2270Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
DMODE_INIT_G	slv ( 1 downto 0 ) := " 00 "
DELAY_INIT_G	Slv5VectorArray ( 0 to 1 , 0 to 7 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32
AXI_CLK_FREQ_G	real := 200 . 0E + 6

Ports
adcCs	out	sl
adcSck	out	sl
adcSdi	out	sl
adcSdo	inout	sl
adcPar	out	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType
status	in	AxiLtc2270StatusType
config	out	AxiLtc2270ConfigType
axiClk	in	sl
axiRst	in	sl
refClk200MHz	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Linear/lct2270/rtl/AxiLtc2270Reg.vhd