TenGigEthGthUltraScaleRst Entity Reference

Inheritance diagram for TenGigEthGthUltraScaleRst:

Collaboration diagram for TenGigEthGthUltraScaleRst:

Entities
TenGigEthGthUltraScaleRst.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns

Ports
coreClk	in	sl
coreRst	in	sl
txGtClk	in	sl
txRstdone	in	sl
rxRstdone	in	sl
phyClk	out	sl
phyRst	out	sl
phyReady	out	sl
extRst	in	sl
coreRst	out	sl
txBufgGtRst	in	sl
qplllock	in	sl
txClk322	in	sl
txUsrClk	out	sl
txUsrClk2	out	sl
gtTxRst	out	sl
gtRxRst	out	sl
txUsrRdy	out	sl
rstCntDone	out	sl

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The documentation for this design unit was generated from the following files:

• ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd
• ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd