TenGigEthGthUltraScaleRst.rtl Architecture Reference

Architecture >> TenGigEthGthUltraScaleRst::rtl

Processes
PROCESS_229	( coreClk )
PROCESS_230	( txClock )

Signals
phyClock	sl
ready	sl
coreReset	sl
phyReset	sl
txClockGt	sl
txClock	sl
txReset	sl
txReady	sl
rstCnt	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
rstPulse	slv ( 3 downto 0 ) := " 1110 "

Instantiations
u_rstsync	RstSync <Entity RstSync>
u_sync	Synchronizer <Entity Synchronizer>
u_corerst	RstPipeline <Entity RstPipeline>
u_phyrst	RstPipeline <Entity RstPipeline>
synchronizer_0	Synchronizer <Entity Synchronizer>
clk312_bufg_gt	bufg_gt
clk156_bufg_gt	bufg_gt
clk156_bufg	bufg
synchronizer_1	Synchronizer <Entity Synchronizer>
synchronizer_2	Synchronizer <Entity Synchronizer>

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The documentation for this design unit was generated from the following files:

• ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleRst.vhd
• ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleRst.vhd