SgmiiDp83867LvdsUltraScale Entity Reference

Inheritance diagram for SgmiiDp83867LvdsUltraScale:

Collaboration diagram for SgmiiDp83867LvdsUltraScale:

Entities
SgmiiDp83867LvdsUltraScale.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>
AxiLitePkg	Package <AxiLitePkg>
EthMacPkg	Package <EthMacPkg>
vcomponents

Generics
TPD_G	time := 1 ns
STABLE_CLK_FREQ_G	real := 156 . 25E + 6
PAUSE_EN_G	boolean := true
JUMBO_G	boolean := true
EN_AXIL_REG_G	boolean := false
PHY_G	natural range 0 to 15 := 3
AXIS_CONFIG_G	AxiStreamConfigType := EMAC_AXIS_CONFIG_C

Ports
extRst	in	sl
stableClk	in	sl
phyClk	out	sl
phyRst	out	sl
localMac	in	slv ( 47 downto 0 )
phyReady	out	sl
linkUp	out	sl
speed10	out	sl
speed100	out	sl
speed1000	out	sl
macClk	in	sl
macRst	in	sl
obMacMaster	out	AxiStreamMasterType
obMacSlave	in	AxiStreamSlaveType
ibMacMaster	in	AxiStreamMasterType
ibMacSlave	out	AxiStreamSlaveType
axilClk	in	sl := ' 0 '
axilRst	in	sl := ' 0 '
axilReadMaster	in	AxiLiteReadMasterType := AXI_LITE_READ_MASTER_INIT_C
axilReadSlave	out	AxiLiteReadSlaveType
axilWriteMaster	in	AxiLiteWriteMasterType := AXI_LITE_WRITE_MASTER_INIT_C
axilWriteSlave	out	AxiLiteWriteSlaveType
phyClkP	in	sl
phyClkN	in	sl
phyMdc	out	sl
phyMdio	inout	sl
phyRstN	out	sl
phyIrqN	in	sl
sgmiiRxP	in	sl
sgmiiRxN	in	sl
sgmiiTxP	out	sl
sgmiiTxN	out	sl

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The documentation for this design unit was generated from the following file:

• devices/Ti/dp83867/lvdsUltraScale/SgmiiDp83867LvdsUltraScale.vhd