RssiCore.rtl Architecture Reference

Architecture >> RssiCore::rtl

Processes
combParamAssign	( closeRq_i , openRq_i , s_appRssiParamReg , s_closeRqReg , s_initSeqNReg , s_intCloseRq , s_modeReg , s_openRqReg )
combParamAssign	( closeRq_i , openRq_i , s_appRssiParamReg , s_closeRqReg , s_initSeqNReg , s_intCloseRq , s_modeReg , s_openRqReg )

Constants
BUFFER_ADDR_WIDTH_C	positive := ( SEGMENT_ADDR_SIZE_G+ WINDOW_ADDR_SIZE_G )

Signals
s_localBusy	sl
s_appRssiParam	RssiParamType
s_rxRssiParam	RssiParamType
s_rssiParam	RssiParamType
s_sndResend	sl
s_sndSyn	sl
s_sndAck	sl
s_sndAckMon	sl
s_sndAckCon	sl
s_sndRst	sl
s_sndNull	sl
s_synHeadSt	sl
s_rstHeadSt	sl
s_dataHeadSt	sl
s_nullHeadSt	sl
s_ackHeadSt	sl
s_txSeqN	slv ( 7 downto 0 )
s_txAckN	slv ( 7 downto 0 )
s_rxLastSeqN	slv ( 7 downto 0 )
s_rxAckN	slv ( 7 downto 0 )
s_rxLastAckN	slv ( 7 downto 0 )
s_headerAddr	slv ( 7 downto 0 )
s_headerData	slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
s_headerRdy	sl
s_txChkEnable	sl
s_txChkValid	sl
s_txChkStrobe	sl
s_txChkLength	positive
s_txChksum	slv ( 15 downto 0 )
s_rxChkEnable	sl
s_rxChkValid	sl
s_rxChkCheck	sl
s_rxChkStrobe	sl
s_rxChkLength	positive
s_rxValidSeg	sl
s_rxDropSeg	sl
s_rxFlags	flagsType
s_rxBufferSize	integer range 1 to 2 ** ( SEGMENT_ADDR_SIZE_G )
s_rxWindowSize	integer range 1 to 2 ** ( WINDOW_ADDR_SIZE_G )
s_rxWrBuffAddr	slv ( BUFFER_ADDR_WIDTH_C- 1 downto 0 )
s_rxWrBuffData	slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
s_rxWrBuffWe	sl
s_rxRdBuffRe	sl
s_rxRdBuffAddr	slv ( BUFFER_ADDR_WIDTH_C- 1 downto 0 )
s_rxRdBuffData	slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
s_txBufferSize	integer range 1 to 2 ** ( SEGMENT_ADDR_SIZE_G )
s_txWindowSize	integer range 1 to 2 ** ( WINDOW_ADDR_SIZE_G )
s_txWrBuffAddr	slv ( BUFFER_ADDR_WIDTH_C- 1 downto 0 )
s_txWrBuffData	slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
s_txWrBuffWe	sl
s_txRdBuffRe	sl
s_txRdBuffAddr	slv ( BUFFER_ADDR_WIDTH_C- 1 downto 0 )
s_txRdBuffData	slv ( RSSI_WORD_WIDTH_C* 8 - 1 downto 0 )
s_rxAck	sl
s_rstFifo	sl
s_sAppAxisMaster	AxiStreamMasterType
s_sAppAxisSlave	AxiStreamSlaveType
s_mAppAxisMaster	AxiStreamMasterType
s_mAppAxisSlave	AxiStreamSlaveType
s_mAppAxisCtrl	AxiStreamCtrlType
s_mAppfifoWrCnt	slv ( SEGMENT_ADDR_SIZE_G downto 0 )
s_sAppSsiMaster	SsiMasterType
s_sAppSsiSlave	SsiSlaveType
s_mAppSsiMaster	SsiMasterType
s_mAppSsiSlave	SsiSlaveType
s_sTspAxisMaster	AxiStreamMasterType
s_sTspAxisSlave	AxiStreamSlaveType
s_mTspAxisMaster	AxiStreamMasterType
s_mTspAxisSlave	AxiStreamSlaveType
s_mTspAxisCtrl	AxiStreamCtrlType
s_sTspSsiMaster	SsiMasterType
s_sTspSsiSlave	SsiSlaveType
s_mTspSsiMaster	SsiMasterType
s_mTspSsiSlave	SsiSlaveType
s_txBufferEmpty	sl
s_lenErr	sl
s_ackErr	sl
s_peerConnTout	sl
s_paramReject	sl
s_initSeqN	slv ( 7 downto 0 )
s_connActive	sl
s_closeRq	sl
s_closed	sl
s_openRq	sl
s_intCloseRq	sl
s_txAckF	sl
s_injectFaultReg	sl
s_injectFault	sl
s_openRqReg	sl
s_closeRqReg	sl
s_modeReg	sl
s_initSeqNReg	slv ( 7 downto 0 )
s_appRssiParamReg	RssiParamType
s_statusReg	slv ( statusReg_o )
s_dropCntReg	slv ( 31 downto 0 )
s_validCntReg	slv ( 31 downto 0 )
s_reconCntReg	slv ( 31 downto 0 )
s_resendCntReg	slv ( 31 downto 0 )
monMasters	AxiStreamMasterArray ( 1 downto 0 )
monSlaves	AxiStreamSlaveArray ( 1 downto 0 )
frameRate	Slv32Array ( 1 downto 0 )
bandwidth	Slv64Array ( 1 downto 0 )
s_txTspState	slv ( 7 downto 0 )
s_txAppState	slv ( 3 downto 0 )
s_txAckState	slv ( 3 downto 0 )
s_rxTspState	slv ( 3 downto 0 )
s_rxAppState	slv ( 3 downto 0 )
s_connState	slv ( 3 downto 0 )

Instantiations
axiliteregitf_inst	RssiAxiLiteRegItf <Entity RssiAxiLiteRegItf>
u_appin	AxiStreamResize <Entity AxiStreamResize>
u_tspin	AxiStreamResize <Entity AxiStreamResize>
connfsm_inst	RssiConnFsm <Entity RssiConnFsm>
monitor_inst	RssiMonitor <Entity RssiMonitor>
headerreg_inst	RssiHeaderReg <Entity RssiHeaderReg>
txfsm_inst	RssiTxFsm <Entity RssiTxFsm>
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
tx_chksum_inst	RssiChksum <Entity RssiChksum>
rxfsm_inst	RssiRxFsm <Entity RssiRxFsm>
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
rx_chksum_inst	RssiChksum <Entity RssiChksum>
appfifoout_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
tspfifoout_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_axistreammon	AxiStreamMon <Entity AxiStreamMon>
axiliteregitf_inst	RssiAxiLiteRegItf <Entity RssiAxiLiteRegItf>
u_appin	AxiStreamResize <Entity AxiStreamResize>
u_tspin	AxiStreamResize <Entity AxiStreamResize>
connfsm_inst	RssiConnFsm <Entity RssiConnFsm>
monitor_inst	RssiMonitor <Entity RssiMonitor>
headerreg_inst	RssiHeaderReg <Entity RssiHeaderReg>
txfsm_inst	RssiTxFsm <Entity RssiTxFsm>
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
tx_chksum_inst	RssiChksum <Entity RssiChksum>
rxfsm_inst	RssiRxFsm <Entity RssiRxFsm>
u_ram	SimpleDualPortRamXpm <Entity SimpleDualPortRamXpm>
u_ram	SimpleDualPortRamAlteraMf <Entity SimpleDualPortRamAlteraMf>
u_ram	SimpleDualPortRam <Entity SimpleDualPortRam>
rx_chksum_inst	RssiChksum <Entity RssiChksum>
appfifoout_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
tspfifoout_inst	AxiStreamFifoV2 <Entity AxiStreamFifoV2>
u_axistreammon	AxiStreamMon <Entity AxiStreamMon>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RssiCore.vhd
• protocols/rssi/v1/rtl/RssiCore.vhd