RssiHeaderReg Entity Reference

Inheritance diagram for RssiHeaderReg:

Entities
RssiHeaderReg.rtl	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
RssiPkg	Package <RssiPkg>
math_real

Generics
TPD_G	time := 1 ns
SYN_HEADER_SIZE_G	natural := 24
ACK_HEADER_SIZE_G	natural := 8
EACK_HEADER_SIZE_G	natural := 8
RST_HEADER_SIZE_G	natural := 8
NULL_HEADER_SIZE_G	natural := 8
DATA_HEADER_SIZE_G	natural := 8

Ports
clk_i	in	sl
rst_i	in	sl
synHeadSt_i	in	sl
rstHeadSt_i	in	sl
dataHeadSt_i	in	sl
nullHeadSt_i	in	sl
ackHeadSt_i	in	sl
busyHeadSt_i	in	sl
ack_i	in	sl
txSeqN_i	in	slv ( 7 downto 0 )
rxAckN_i	in	slv ( 7 downto 0 )
headerValues_i	in	RssiParamType
addr_i	in	slv ( 7 downto 0 )
headerData_o	out	slv ( ( RSSI_WORD_WIDTH_C* 8 ) - 1 downto 0 )
ready_o	out	sl
headerLength_o	out	positive

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/RssiHeaderReg.vhd
• protocols/rssi/v1/rtl/RssiHeaderReg.vhd